9.5 A 249Mpixel/s HEVC Video-Decoder Chip for Quad Full HD Applications
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چکیده
The latest video coding standard High Efficiency Video Coding (HEVC) [1] provides 50% improvement in coding efficiency compared to H.264/AVC, to meet the rising demand for video streaming, better video quality and higher resolutions. The coding gain is achieved using more complex tools such as larger and variable-size coding units (CU) in a hierarchical structure, larger transforms and longer interpolation filters. This paper presents the first integrated circuit which supports Quad Full HD (QFHD, 3840x2160) video decoding for HEVC draft standard. It addresses new design challenges for HEVC (“H.265”) with three primary contributions: 1) a system pipelining scheme which adapts to the variable-size largest coding unit (LCU) and provides a twostage sub-pipeline for memory optimization; 2) unified processing engines to address hierarchical coding structure and many prediction and transform block sizes in area-efficient ways; 3) a motion compensation (MC) cache which reduces DRAM bandwidth for the large LCU and meets the high throughput requirement due to long filters.
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تاریخ انتشار 2012